The present invention relates to a semiconductor device and system.
A system on chip (to be referred to as an SoC hereinafter) contains a plurality of system modules having different calculating functions, and receives an externally supplied power supply voltage VEX.
The system modules are connected by a system bus, and exchange data via the system bus. The system modules also exchange data with devices outside the chip via an input/output interface circuit.
Assume that the SoC contains two system modules 1 and 2, and the processing speed of system module 2 is higher than that of system module 1.
This SoC has, e.g., two power supply circuits 1 and 2, and power supply circuit 1 generates a predetermined internal power supply voltage (low voltage) VIN1 as the operating voltage of system module 1.
Similarly, power supply circuit 2 generates a predetermined internal power supply voltage (high voltage) VIN2 as the operating voltage of system module 2.
The internal power supply voltage VIN2 is higher than the internal power supply voltage VIN1 because system module 2 is required to have a processing speed higher than that of system module 1.
That is, the higher the power supply voltage, the higher the transmission rate of a logic circuit. Therefore, system module 2 requires a higher internal power supply voltage VIN2 in order to achieve a higher processing speed.
On the other hand, the lower the internal power supply voltage VIN, the smaller the power consumption of the module. Accordingly, the power consumption of the whole chip can be minimized by optimizing the internal power supply voltage VIN such that a speed equal to or slightly higher than the necessary processing speed is realized.
Conventionally, however, power supply control of the semiconductor device is performed as follows.
N- and P-channel MOS transistors are connected in parallel between an external terminal for inputting the external power supply voltage VEX and an internal power supply voltage output terminal for generating the internal power supply voltage VIN.
When the N-channel MOS transistor is turned off and the P-channel MOS transistor is turned on, a voltage sufficiently higher than the threshold voltage can be applied to the gate-to-source path by applying 0 V to the gate of the P-channel MOS transistor. As a consequence, the internal power supply voltage VIN has substantially the same electric potential as the external power supply voltage VEX.
The control is as follows, however, when the P-channel MOS transistor is turned off and only the N-channel MOS transistor is turned on.
When the gate of the N-channel MOS transistor is controlled by a gate, potential VG, the internal power supply voltage VIN is controlled such that VIN=VG−VTH<VEX where VTH is the threshold voltage of the N-channel MOS transistor, regardless of the external power supply voltage VEX.
Note that to stably generate the internal power supply voltage VIN lower than the external power supply voltage VEX by using the N-channel MOS transistor, the internal power supply voltage VIN must be lower by about 200 mV or more than the external power supply voltage VEX, since a resistance exists between the source and drain of the N-channel MOS transistor.
When the external power supply voltage VEX is, e.g., 1.5 V, therefore, the internal power supply voltage VIN is 1.3 V if the N-channel MOS transistor alone is turned on.
Consequently, it is possible to generate only two types of voltages, i.e., 1.5 V when the P-channel MOS transistor is turned on, and 1.3 V or less when the N-channel MOS transistor alone is turned on.
Accordingly, if the voltage at which the processing speed of the system is maintained and the power consumption is optimum is 1.4 V, the power consumption cannot be minimized because no such voltage can be generated.
In addition, the necessary internal power supply voltage of the system module changes in accordance with, e.g., the operation environment such as the temperature and variations in process parameters. Since only two different internal power supply voltages can be generated, the internal power supply voltage is determined in accordance with conditions which maximize the processing speed of the system module. This poses the problem that the electric power is wastefully consumed.
The following is a reference disclosing the power supply control technique in the conventional semiconductor device.
Reference 1: Japanese Patent Laid-Open No. 11-224141